RESEARCH
Current Objectives
Modern integrated chips continue to face trade-offs between power dissipation and computation capability. Our goal is to alleviate this trade off issue allowing self adapting asynchronous computation in the parallel processing domain. Our lab is pursuing following areas of research to lay the foundations to achieve our goals.
Embedded Memory Interface
- > Special purpose memories in DRAM process technology
- > Power efficient memory buffers for high performance graphics systems.
- > Area efficient image processing memory buffers
Asynchronous Clocking Interface
- > Asynchronous data transmission and recovery protocol
- > Clock and data recovery circuits suitable for asynchronous computation.
- > Adaptive transmission rate optimizing architecture for power reduction
Low Power Parallel Processor Interface
- > Processor architectures suitable for high band-width memory interface
- > Intercommunication strategies for efficient processors utilization.
Mixed Mode Reconfigurable Interface
- > Integration of reconfigurable digital systems with reconfigurable analog circuitry
- > Intelligent analog circuit test circuitry